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Cadence SP&R Design Tools Used by Fujitsu to Tape-Out 1.6 Million Gate, 266 MHz Embedded Microprocessor
SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 17, 2001--
Cadence Design Systems, Inc. (NYSE:CDN), the world's leading
supplier of electronic design products and services, today announced
the successful design and tape-out of the FR500 microprocessor by the
Fujitsu Limited Electronic Devices Group using Cadence® SP&R
(synthesis/place-and-route) design tools. The Fujitsu FR-V processor
design team used Cadence Physically Knowledgeable Synthesis (PKS)
physical synthesis and Silicon Ensemble(TM) PKS (SE-PKS) optimization
place-and-route design tools to achieve the highest frequency Fujitsu
very long instruction word (VLIW) architecture embedded microprocessor
to date.
``Our engineers have verified that PKS meets timing constraints for
the latest product of the FR500 series processor in 0.18 micron
technology,'' said Takao Sukemura, project manager of the System
Solution LSI Division, Electronic Devices Group, Fujitsu Ltd. ``Using
PKS in an automated design flow, we were able to achieve a clock speed
of 266 MHz while reducing overall design turn-around time. The
physically knowledgeable synthesis of PKS allowed us to meet timing
closure on this processor by closing the gap between pre-route and
post-route timing.''
This embedded microprocessor will be used in Internet terminal
technology, printers, fax machines, digital television components, and
consumer multimedia set top box systems for receiving and decoding
digital broadcasting signals. PKS was used on eight floorplan blocks,
up to 200,000 gates each, representing the overwhelming majority of
the random logic in the 1.6 million-gate integrated circuit design.
The margin of error in correlation between PKS and post-route timing
was less than two percent. PKS and SE-PKS helped eliminate iterations
and reduce design time by six weeks.
``Fujitsu's successful use of Cadence's front-to-back SP&R
technology on one of their premier processors is further evidence of
the impact that SP&R is making on leading-edge IC designs worldwide,''
said Jeff Roane, vice president of SP&R marketing at Cadence.
About Cadence SP&R
Cadence SP&R consists of three products, Ambit® BuildGates®
synthesis, PKS physical synthesis, and Silicon Ensemble PKS
optimization place-and-route. This SP&R solution is superior to
heterogeneous IC design environments, as it features correlation
within three percent through common timing, synthesis, placement, and
routing engines used by both logic designers and physical designers.
About PKS Physical Synthesis
PKS is the most complete and tightly integrated physical synthesis
solution on the market. It achieves tight correlation with final
routed results because its synthesis, timing, placement, and true
global routing engines are integrated into the same tool. This
integration also provides better quality of results, seen in the
frequency and area of the design.
About Silicon Ensemble PKS Optimization Place-and-Route
Silicon Ensemble PKS (SE-PKS) uses Cadence PKS technology to
completely restructure gate-level netlists produced by conventional
wireload-model-based synthesis. It can also directly read PKS
databases that contain placement and global routing information,
making it the only place-and-route tool that can accept
forward-annotated global routing. SE-PKS is a comprehensive
place-and-route tool that incorporates enhanced industry-standard
constraint support, which makes it much easier to move designs from
conventional synthesis into place-and-route, and to adopt a
timing-driven design flow.
Pricing and Availability
Cadence PKS physical synthesis and SE-PKS optimization
place-and-route are available for UNIX-based workstations from
Hewlett-Packard and Sun Microsystems, and for AIX-based workstations
from IBM. One-year U.S. list prices start at $100,000 and $400,000,
respectively. For information on international pricing, please contact
the local Cadence sales office.
About Cadence
Cadence is the largest supplier of electronic design automation
products, methodology services, and design services used to accelerate
and manage the design of semiconductors, computer systems, networking
and telecommunications equipment, consumer electronics, and a variety
of other electronics-based products. With approximately 5,200
employees and 1999 annual revenue of $1.1 billion, Cadence has sales
offices, design centers, and research facilities around the world. The
company is headquartered in San Jose, Calif., and traded on the New
York Stock Exchange under the symbol CDN. More information about the
company, its products, and its services may be obtained from the World
Wide Web at http://www.cadence.com.
Note to Editors: Cadence, the Cadence logo, Ambit, and BuildGates
are registered trademarks, and Silicon Ensemble is trademarks of
Cadence Design Systems, Inc. All other trademarks are the property of
their respective owners.
Contact:
Cadence Design Systems, Inc., San Jose
Judy Erkanat, 408/894-2302
jerkanat@cadence.com
or
Armstrong Kendall, Inc.
Matt McGinnis, 503/672-4689
matt@akipr.com
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